White Papers, Editorials & Technical Papers
Why Upgrade to Akrometrix Studio?
Introduction to High Volume Testing with Part Tracking™ in Akrometrix Studio 6.0
Akrometrix Testing Applications
Die and Package Testing Protocol/Best Practices
PCB Testing Protocol/Best Practices
Socket Testing Protocol Summary
The Lead-Free "Whac-A-Mole"
Ron Leckie, President, INFRASTRUCTURE Advisors
Ready to Start Measuring PCB Warpage
Ken Chiavone, John Davignon
PCB Dynamic Coplanarity at Elevated Temperatures
iNEMI SMT Coplanarity Workgroup
John Davignon, Ken Chiavone, Jiahui Pan, James Henzi, David Mendez, Ron Kulterman
Advanced Second Level Assembly Analysis Techniques - Troubleshooting Head-In-Pillow, Opens, and Shorts with Dual Full-Field 3D Surface Warpage Data Sets
As originally published in IPC APEX EXPO 2013 Proceedings
Ken Chiavone
Generalizations about Component Flatness at Elevated Temperature
As originally published in Toronto International Conference on Soldering and Reliability 2013
Bev Christian, Linda Galvis, Rick Shelley and Matthew Anthony
Double Reflow-Induced Brittle Interfacial Failures in Pb-free Ball Grid Array Solder Joints
As originally published in IPC APEX EXPO 2013 Proceedings
Julie Silk, George Wenger, Richard Coyle, Jon Goodbread, Andrew Giamis
Correlation of Solder Joint Reliability of µPGA Socket To Package Flatness and PCB Warpage
Dr. Paul P.E. Wang, Shlomo Novotny, Keith Graveling, Damian Hujic, Dr. Dereje Agonafer and Wonkee Ahn.
Comparing Techniques for Temperature-Dependent Warpage Measurement
Jiahui Pan, Ryan Curry, Neil Hubble, Dirk Zwemer
CSP Board Level Reliability - Results
H.J. Albrecht, G. Petzold, B. Schwarz, H. Teichmann
Thinking Globally, Measuring Locally
Patrick Hassell
Measurement of Thermally Induced Warpage of BGA Packages/Substrates Using Phase-Stepping Shadow Moiré
Yinyan Wang, Patrick Hassell
A Study on Package Stacking Process for Package-on-Package (PoP)
Akito Yoshida, Jun Taniguchi, Katsumasa Murata, Morihiro Kada, Yusuke Yamamoto, Yoshinori Takagi, Takeru Notomi, Asako Fujit
Effect of Printed Wiring Board Warpage on Ball grid Arrays over Temperature
Kyra Ewer and Jeffrey Seekatz
FEA Simulation and In-situ Warpage Monitoring of Laminated Package Molded with Green EMC Using Shadow Morie System
Zhao Baozong, Vivek Pai, Chinnu Brahateeswaran, Hu Guojun, Spencer Chew, Neephing Chin
Effect of Geometry and Temperature Cycle on the Reliability of WLCSP Solder Joints
Satish C. Chaparala, Brian D. Roggeman, James M. Pitarresi, Bahgat G. Sammakia, John Jackson, Garry Griffin, Tom McHugh
Advanced Warpage Characterization: Location and Type of Displacement can be Equally Important as Magnitude
Patrick Hassell
Survey of Circuit Board Warpage During Reflow
Michael J. Varnau
Measurement of Deformation and Strain in Flip Chip on BGA (FC-BGA)
L. Kehoe, V. Guenebaut, P.V. Kelly
Measuring board and component flatness
Patrick B. Hassell, Thomas E. Adams
New Package/Board Materials Technology for Next-Generation Convergent Microsystems
Nitesh Kumbhat, P. Markondeya Raj, Shubhra Bansal, Ravi Doraiswami, S. Bhattacharya and Rao Tummala
Quantitative Classification of Saw Marks of Silicon Wafers
A. Lawerenz, S. Dauwe, F.W. Schulze
Warpage Studies of HDI Test Vehicles
Gregory J. Petriccione, I. Charles Ume, Ph.D.
Traceability on the Line
Compiled by SMT
Shadow Moiré Enters Production
Kathleen McCray
Controlling bow and twist
Bob Willis
Elevated Temperature Measurements of Warpage of BGA Packages
David W. Garrett